Conference paper Gold Open Access 2020

Towards sustainable integrated model for skill development: A collaborative approach

SS
Siddamal, Saroja V.
 SS
Shirol, Suhas B.
 HS
Hiremath, Shraddha Balayya
 IN
Iyer, Nalini C.
Procedia Computer Science
Conference · Vol. 172 · pp. 460-467
Abstract

Employability of Engineering graduates and their ability to deliver to the VLSI industry expectations after they are hired has been a matter of concern, engaging the attention of academics and industry alike on this issue. It is not a problem of quantity that the industry is facing but it is a problem of quality - the quality of VLSI education and quality of students getting through engineering institutions is poor. The important problem is, most VLSI companies are reluctant to hire freshers. This is because only few colleges in India have the infrastructure or specific courses related to VLSI domain. Universities don't have specific courses related to VLSI in their curriculum. The solution for this employability issue is to offer good quality VLSI education with live hands on projects. In India VLSI talent is in short supply, it is not a problem of quantity, but the quality.The solution is to offer good quality VLSI education. To address these issues KLE Tech-IESA-SEER has collaborated for promoting skill set requirement through a set of courses. The courses are designed, delivered and assessed by in-house and industry-expert to build competence. The success story is the extensive industrial experience, internship opportunity and job in VLSI core companies. © 2020 The Authors. Published by Elsevier B.V.

Keywords

Author Keywords

Internship employability Collaborations Skill Set VLSI Talent

Index Keywords

Curricula Engineering education Education computing Students employability Internship Skills development Engineering graduates Skill sets Collaboration VLSI circuits Collaborative approach Course related Integrated modeling VLSI talent
Author Affiliations
School of Electronics and Communication Engineering, KLE Technological University, Hubli, KA, India
Funding & Acknowledgements
International Foundation for Research in Paraplegia, IRP
The authors would like to thank Dr. Anand Bariya, VP SiFive, for his valuable discussion on the mixed signal ASIC flow, Shri Shripad Annigari for his valuable discussion on circuits and Mentor Graphic for Calibre Tool support. This work is supported under 'Institutional Research Project (IRP)' scheme by the KLE Technological University.
References 8 References
1 International Journal of Arts and Commerce, (2013)
2 Barthorpe, Stephen, A collaborative approach to placement preparation and career planning for university students: A case study, Journal of Vocational Education and Training, 52, 2, pp. 165-175, (2000)
3 Othman, Hasyamuddin, Engineering Students: Enhancing Employability Skills through PBL, IOP Conference Series: Materials Science and Engineering, 203, 1, (2017)
4 undefined
5 2nd International Conference on Transformations in Engineering Education Ictiee 2016
6 3rd International Conference on Transformations in Engineering Education Ictiee 2017
7 Zaharim, Azami, Practical framework of employability skills for engineering graduate in Malaysia, 2010 IEEE Education Engineering Conference, EDUCON 2010, pp. 921-927, (2010)
8 Siddamal, Saroja V., Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology, Communications in Computer and Information Science, 1066, pp. 126-140, (2019)
Quick Actions
Full Text via DOI
Citation Metrics
5
Times Cited (Scopus)
References 8
Document Identifiers